With the continuous development of the semiconductor technology, the technical node of the semiconductor process has become smaller and smaller. In order to obtain a desired threshold voltage and to improve the performance of devices, the gate-last process has been widely used. However, when the critical dimension (CD) of the semiconductor devices is further reduced, the structures of the conventional MOS field-effect transistors (MOSFETs) are unable to match the performance requirements even the gate-last process is used to form the MOSFETs. Thus, Fin Field-Effect transistors (Fin FETs), a substitution of the conventional MOSFETs, have attracted extensive attentions.
FIG. 1 illustrates a FinFET formed by an existing fabrication process. As shown in FIG. 1, the FinFET includes a semiconductor substrate 10 and a protruding fin 14 formed on the semiconductor substrate 10. The fin 14 is usually formed by etching the semiconductor substrate 10. The FinFET also includes an isolation layer 11 covering the surface of the semiconductor substrate 10 and a portion of the side surfaces of the fin 14. Further, the FinFET includes a gate structure 12 stretching over the fin 14 and covering the top surface of the fin 14 and the side surfaces of the fin 14. The gate structure 12 includes a gate dielectric layer 15 and a gate electrode 16 formed on the gate dielectric layer 15.
The gate dielectric layer 15 is made of silicon oxide; and the gate electrode 16 is often made of polysilicon. When the CD of the FinFETs is continuously reduced with the development of the semiconductor technology, in order to lower the parasitic capacitance; reduce the leakage current; and increase the device speed, high-K metal gate (HKMG) structures have been adapted into the FinFETs to substitute the conventional gate structure. The HKMG structure is a stacked gate structure having a high dielectric constant (high-K) gate dielectric layer and a metal gate. In order to prevent the metal material of the metal gate from affecting the properties of other structures of the FinFETs, the HKMG structure is usually formed by a gate-last process.
An existing gate-last process for forming FinFETs with the HKMG structures includes providing a semiconductor substrate; and forming a plurality of fins on the semiconductor substrate. The process also includes forming dummy gates on the surfaces of the fins; and forming a dielectric layer to cover the dummy gates, the fins, and the surface of the semiconductor substrate. The surface of the dielectric layer is higher than the surface of the top surfaces of the dummy gates. Further, the process includes planarizing the dielectric layer by a chemical mechanical polishing (CMP) process until the top surface of the dummy gate is exposed; and removing the dummy gates to form openings exposing portions of the top surfaces and side surfaces of the fin. Further, the process also includes forming a high-K dielectric layer in the openings and the forming a metal gate on the high-K dielectric layer.
However, when using such process, it may be easy to form void defects in the dielectric layer. Thus, the electrical insulating characteristic of the dielectric layer may be significantly affected. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.